The present invention generally relates to microelectronic packages and more particularly relates to microelectronic packages fabricated at the wafer level and to methods of making such packages.
Semiconductor chips are flat bodies with contacts disposed on the front surface that are connected to the internal electrical circuitry of the chip itself. Semiconductor chips are typically packaged with substrates to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit, e.g., a circuit in an electronic product such as a computer or a cell phone.
The substrate materials used for packaging semiconductor chips are selected for their compatibility with the processes used to form the packages. For example, during solder or other bonding operations, intense heat may be applied to the substrate. Accordingly, metal lead frames have been used as substrates. Laminate substrates have also been used to package microelectronic devices. Such substrates may include two to four alternating layers of fiberglass and epoxy, wherein successive fiberglass layers may be laid in traversing, e.g., orthogonal, directions. Optionally, heat resistive compounds such as bismaleimide triazine (BT) may be added to such laminate substrates.
Tapes have been used as substrates to provide thinner microelectronic packages. Such tapes are typically provided in the form of sheets or rolls of sheets. For example, single and double sided sheets of copper-on-polyimide are commonly used for fine-line and high-density electronic interconnection applications. Polyimide based films offer good thermal and chemical stability and a low dielectric constant, while copper having high tensile strength, ductility, and flexure has been advantageously used in both flexible circuit and chip sized packaging applications. However, such tapes are relatively expensive, particularly as compared to lead frames and laminate substrates.
Depending on the configuration and other requirements of the microelectronic package, different substrate materials may be used. For example, in a flip-chip configuration, the front or contact-bearing surface of the microelectronic device faces towards a substrate. Each contact on the device is joined by a solder bond to a corresponding contact pad on the substrate, by positioning solder balls on the substrate or device, juxtaposing the device with the substrate, and momentarily reflowing the solder. Flip-chip configurations, however, may encounter problems in thermal expansion mismatch. When the coefficient of thermal expansion (CTE) for the device differs significantly from the CTE for the substrate, the solder connections will undergo fatigue when the package is thermally cycled. This is particularly problematic for flip-chip packages with fine pitch, small bumps, and/or large device footprints. Thus, to enhance reliability, the substrate is typically selected so that the CTE of the substrate closely matches the CTE of the device.
To improve productivity and reduce costs associated with microelectronic manufacturing, there have been many efforts directed to forming microelectronic packages at the wafer-scale level. Wafer-scale assemblies allow a plurality of devices in the form of a wafer to be packaged with a substrate as a single structure. Once formed, the wafer-scale structure is diced and separated into individual packages. However, problems associated with CTE mismatch between the wafer and the substrate are exacerbated due to the size of the wafer-scale structure. Thus, wafer-scale manufacturing of microelectronic packages may require exceptionally close matching of the CTE of the device and the substrate.
U.S. Pat. No. 6,753,208 to MacIntyre describes a chip scale package structure formed by adhering a glass sheet having a pattern of holes matching a pattern of bond pads on a semiconductor wafer so that the pattern of holes on the glass sheet are over the pattern of bond pads on the semiconductor wafer. Metallized pads are formed on the glass sheet adjacent each hole. A conductive trace is formed from each metallized pad on the glass sheet to the bond pad on the semiconductor wafer under the adjacent hole. In addition, the pad extends down the sides of the adjacent hole, which is then filled with a metal plug that electrically connects the pad on the glass sheet to the bond pad on the semiconductor wafer.
In certain embodiments of commonly assigned U.S. patent application Ser. No. 11/025,432, filed Dec. 29, 2004, the disclosure of which is hereby incorporated by reference herein, a microelectronic package includes a microelectronic device, a unitary ceramic substrate, and a plurality of terminals. The microelectronic device has a substantially planar front surface and a plurality of electrical contacts thereon. The substrate has a first substantially planar surface and a second surface opposing the first surface. A window extends from a first opening on the first surface and along a side wall to a second opening on the second surface. A conductive region may be provided on the side wall and/or the second substrate surface. Typically, but not necessarily, the window has varied cross-sectional areas along its lumen as defined by its side wall. The substrate is located between the device and the terminals such that the first surface of the substrate faces the front surface of the device and the first opening is aligned with at least one contact on the front device surface.
The device and the substrate disclosed in the '432 application may be coupled or decoupled to each other. However, there is typically substantially no void between the first surface of the substrate and the front surface of the device. For example, an adhesive may be provided between the device and the substrate. In addition, the package may include a compliant layer between the device and at least one terminal, e.g., between the at least one terminal and the substrate and/or between the device and the substrate. Accordingly, one or more terminals and the substrate may be coupled or decoupled to each other.
The device contacts of the '432 application electrically communicate with the terminals in any of a number of ways. For example, one or more device contacts may be provided in electrical communication with at least one terminal through the window via one or more conductive regions. This may be achieved by lead bonding or wire bonding the contacts to the conductive region. Once electrical communication is achieved, an encapsulant may be dispensed into the window, optionally filling the window to a substantially void-free degree.
In further embodiments of the '432 application, a wafer-scale microelectronic assembly includes a wafer and a unitary ceramic substrate. The wafer includes an array of microelectronic devices each having a coplanar front surface and a plurality of electrical contacts thereon. The ceramic substrate has a first substantially planar surface and a second surface opposing first surface. One or more windows extend from a first opening on the first surface along a side wall to a second opening on the second surface. The windows may or may not have varied cross-sectional areas. One or more conductive regions are located on at least one side wall or the second surface. The first surface of the substrate faces the front device surfaces, and each first opening is aligned with at least one electrical contact, typically on different devices. When the wafer has a diameter of at least 200 mm, the substrate and the device may have coefficients of thermal expansion that differ by less than about 3.0 ppm/° C. In other embodiments, the substrate and the device may have coefficients of thermal expansion that differ by less than about 0.1 ppm/° C.
Microelectronic packages also include wafer level packages, which provide an enclosure for a semiconductor component that is fabricated while the die are still in a wafer form. The wafer is subject to a number of additional process steps to form the package structure and the wafer is then diced to free the individual die, with no additional fabrication steps being necessary. Wafer level processing provides an advantage in that the cost of the packaging processes are divided among the various die on the wafer, resulting in a very low price differential between the die and the component. Furthermore, the package footprint is identical to the die size, resulting in very efficient utilization of area on a printed circuit board (PCB) to which the die will eventually be attached. As a result of these features, die packaged in this manner are commonly referred to as wafer level chip sized package (WLCSP).
FIG. 1 shows a conventional wafer level chip sized package 20 including a silicon wafer 22 having a top surface 24 with contacts 26 and a bottom surface 28 remote from the top surface 24. The wafer level chip sized package includes a passivation layer 30 formed atop the first surface 24 of the wafer 22. A resin layer 32 is then formed atop the passivation layer 30, and conductive traces 34 are deposited atop the resin layer 32. A second resin layer 36 having one or more openings 38 is deposited over the conductive traces 34 and the first resin layer 32. Conductive masses such as solder bumps 40 may be placed through openings 38 for forming an electrical interconnection with the conductive trace 34.
Conventional wafer level packages share a common trait in that the elements required to form the package structure are built on the surface of the semiconductor wafer. This approach has the drawback that the finished high-value semiconductor wafer is subject to an appreciable number of additional process steps. Thus, a process failure during any one of the packaging steps risks loss of the entire wafer. Thus, there is a need for an alternative approach to building most of the elements of wafer level packages so as to avoid loosing entire wafers during the packaging processes.
In spite of the above advances, there remains a need for improved wafer-scale packages that are cheaper, smaller and lighter and to methods of manufacturing such wafer-scale packages that are economical and reliable.